A prior partitioned system is disclosed in U.S. Pat. No. 4,843,541 to Bean et al, which is assigned to the same assignee as the subject invention. In that patent, each partition (called a "zone") in the system supports a respective guest operating system (called a "guest"), which may be a copy of the IBM MVS or VM operating system. A hypervisor program (called the "host") supervises all guest operating systems in the different partitions of the system.
The description in U.S. Pat. No. 4,843,541 limits the maximum number of partitions in the system to the maximum number of I/O interruption subclasses (ISCs) available in the pending register in each CPU in the system, which enabled a total of eight I/O interruption subclasses (ISCs) to be used. Each ISC corresponds to an I/O interruption queue which receives a subset of I/O interruptions from a designated subset of I/O devices. A pending register in each CPU having a maximum of eight ISC positions was the physical interface of the CPU to the I/O interruptions pending in the system. The drawings and specification of U.S. Pat. No. 4,843,541 are incorporated herein by reference.
U.S. Pat. No. 4,271,468 to N.T. Christensen et al discloses and claims the use of a pending register in each CPU for indicating to the CPU whether any I/O interruption exists in corresponding I/O interruption queue subclasses. The pending register enables a CPU to know of the existence of pending I/O interruptions in respective ISC queues and allows the CPU to prioritize the pending interruptions for controlling the dispatching of programs on the CPU. The drawings and specification of U.S. Pat. No. 4,271,468 are incorporated herein by reference.
However, the U.S. Pat. No. 4,843,541 disclosure has the limitation of one host controlled ISC per partition for handling all guest I/O interruptions in the partition. This limitation occurs via a mechanism called an EIEM (effective I/O enablement mask). This limitation resulted in: 1. the system having a maximum of eight zones. (corresponding to the eight ISC positions in each CPU pending register, and 2. each guest losing some ISC priority granularity among its guest I/O interruptions.
The use of one host ISC per guest operating system forces all of the I/O interruptions of each guest to funnel through one assigned host ISC (regardless of which of up to eight different guest I/O queues may have received an I/O interruption). Only the host ISC was available to control the dispatching of each guest's program on the CPUs in the system. Thus, the eight ISC positions in the EIEM (corresponding to the eight ISC positions in the CPU's pending register) caused the limitation of the eight partition (zone) maximum in the system, and further limited each guest to only one effective ISC.
A hypervisor software program, called the host, provides overall control of the system, and the host communicates with the guests by guest operations providing special exception signals in the system.
Zones include areas in system main storage respectively assigned to the logical partitions configured from all of the resources of a Central Electronics Complex (CEC). The CPU resources in the CEC are not usually dedicated to any single partition. And, the CPUs are usually temporarily assigned to all partitions by dispatching a CPU for a partition that has a program ready to execute with the resources available in that partition. Each partition uses a software system--usually an operating system--that controls the operation of all programs in a partition; and it is the guest in the partition. Thus, each partition is defined as a subset of the CEC's resources assigned to it. Guests may be dispatched on any CPU in the system by the CPU executing the IBM ESA/390 start interpretive execution (SIE) instruction. Guest execution on a CPU ends each time the SIE state of the guest is ended (SIE is intercepted).
Each guest operating system in turn can dispatch virtual processors (and virtual multi-processors, MPs) in its partition using the SIE instruction in the ESA/390 architecture. And the dispatched virtual processors can then execute application programs on the real CPUs on which the guests are dispatched. An application program is accessed in system memory through the guest PSW. The guest's PSW is initialized from the guest's SD (state description). The SD is the operand of the SIE instruction which the host uses to dispatch a guest.
A pageable-storage mode is used for V=V guests, in which the guest's absolute storage is mapped contiguously onto the virtual storage of the host. The host DAT (dynamic address translation) facility handles the V=V guest absolute storage as a host virtual space. A preferred guest (V=F guest) is mapped directly onto the host's absolute storage, using an offset and limit absolute address for each guest to locate the guest zones in system memory. A V=R guest is a special case of a V=F guest in which the offset is zero.